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1 features ? fast read access time - 70 ns 5-volt only reprogramming page program operation ? single cycle reprogram (erase and program) ? internal address and data latches for 64 bytes internal program control and timer hardware and software data protection fast program cycle times ? page (64 byte) program time - 10 ms ? chip erase time - 10 ms data polling for end of program detection low-power dissipation ? 50 ma active current ? 300 a cmos standby current typical endurance > 10,000 cycles single 5v 10% supply cmos and ttl compatible inputs and outputs commercial and industrial temperature ranges description the at29c256 is a five-volt-only in-system flash programmable and erasable read only memory (perom). its 256k of memory is organized as 32,768 words by 8 bits. manufactured with atmel ? s advanced nonvolatile cmos technology, the device offers access times to 70 ns with power dissipation of just 275 mw. when the device is deselected, the cmos standby current is less than 300 a. the device endurance is such that any sector can typically be written to in excess of 10,000 times. 256k (32k x 8) 5-volt only flash memory at29c256 rev. 0046n ? 08/99 pin configurations pin name function a0 - a14 addresses ce chip enable oe output enable we write enable i/o0 - i / o7 data inputs/outputs nc no connect dc don ? t connect tsop top view type 1 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 oe a11 a9 a8 a13 a14 vcc we a12 a7 a6 a5 a4 a3 a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 plcc and lcc top view note: plcc package pins 1 and 17 are don ? t connect. 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a6 a5 a4 a3 a2 a1 a0 nc i/o0 a8 a9 a11 nc oe a10 ce i/o7 i/o6 4 3 2 1 32 31 30 14 15 16 17 18 19 20 i/o1 i/o2 gnd dc i/o3 i/o4 i/o5 a7 a12 we dc vcc a14 a13 dip top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 we a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vcc a14 a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 (continued)
at29c256 2 to allow for simple in-system reprogrammability, the at29c256 does not require high input voltages for pro- gramming. five-volt-only commands determine the opera- tion of the device. reading data out of the device is similar to reading from a static ram. reprogramming the at29c256 is performed on a page basis; 64 bytes of data are loaded into the device and then simultaneously pro- grammed. the contents of the entire device may be erased by using a six-byte software code (although erasure before programming is not needed). during a reprogram cycle, the address locations and 64 bytes of data are internally latched, freeing the address and data bus for other operations. following the initiation of a program cycle, the device will automatically erase the page and then program the latched data using an internal control timer. the end of a program cycle can be detected by data polling of i/o7. once the end of a program cycle has been detected a new access for a read, program or chip erase can begin. block diagram device operation read: the at29c256 is accessed like a static ram. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in preventing bus contention. byte load: a byte load is performed by applying a low pulse on the we or ce input with ce or we low (respec- tively) and oe high. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . byte loads are used to enter the 64 bytes of a page to be programmed or the software codes for data protection and chip erasure. program: the device is reprogrammed on a page basis. if a byte of data within a page is to be changed, data for the entire page must be loaded into the device. any byte that is not loaded during the programming of its page will be indeterminate. once the bytes of a page are loaded into the device, they are simultaneously programmed during the internal programming period. after the first data byte has been loaded into the device, successive bytes are entered in the same manner. each new byte to be programmed must have its high-to-low transition on we (or ce ) within 150 s of the low-to-high transition of we (or ce ) of the preceding byte. if a high-to-low transition is not detected within 150 s of the last low-to-high transition, the load period will end and the internal programming period will start. a6 to a14 specify the page address. the page address must be valid during each high-to-low transition of we (or ce ). a0 to a5 specify the byte address within the page. the bytes may be loaded in any order; sequential loading is not required. once a programming operation has been initiated, and for the duration of t wc , a read operation will effectively be a polling operation. software data protection: a software controlled data protection feature is available on the at29c256. once the software protection is enabled a software algorithm must be issued to the device before a program may be per- formed. the software protection feature may be enabled or disabled by the user; when shipped from atmel, the soft- ware data protection feature is disabled. to enable the soft- ware data protection, a series of three program commands to specific addresses with specific data must be performed. after the software data protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. all software program commands must obey the page program timing specifica- tions. once set, the software data protection feature remains active unless its disable command is issued. power transitions will not reset the software data protection feature, however the software feature will guard against inadvertent program cycles during power transitions.
at29c256 3 once set, software data protection will remain active unless the disable command sequence is issued. after setting sdp, any attempt to write to the device without the three-byte command sequence will start the internal write timers. no data will be written to the device; however, for the duration of t wc , a read operation will effectively be a polling operation. after the software data protection ? s three-byte command code is given, a byte load is performed by applying a low pulse on the we or ce input with ce or we low (respec- tively) and oe high. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . the 64 bytes of data must be loaded into each sector by the same proce- dure as outlined in the program section under device operation. hardware data protection: hardware features protect against inadvertent programs to the at29c256 in the following ways: (a) v cc sense ? if v cc is below 3.8v (typical), the program function is inhibited; (b) v cc power on delay ? once v cc has reached the v cc sense level, the device will automatically time out 5 ms (typical) before pro- gramming; (c) program inhibit ? holding any one of oe low, ce high or we high inhibits program cycles; and (d) noise filter ? pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle. product identification: the product identification mode identifies the device and manufacturer and may be accessed by a hardware operation. for details, see oper- ating modes or product identification. data polling: the at29c256 features data polling to indicate the end of a program cycle. during a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on i/o7. once the pro- gram cycle has been completed, true data is valid on all outputs and the next cycle may begin. data polling may begin at any time during the program cycle. toggle bit: in addition to data polling the at29c256 provides another method for determining the end of a pro- gram or erase cycle. during a program or erase operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examining the toggle bit may begin at any time during a program cycle. optional chip erase mode: the entire device can be erased by using a six-byte software code. please see software chip erase application note for details. absolute maximum ratings* temperature under bias................................ -55 c to +125 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe with respect to ground ...................................-0.6v to +13.5v
at29c256 4 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. 4. manufacturer code: 1f, device code: dc. 5. see details under software product identification entry/exit. dc and ac operating range at29c256-70 at29c256-90 at29c256-12 at29c256-15 operating temperature (case) com. 0 c - 70 c0 c - 70 c0 c - 70 c0 c - 70 c ind. -40 c - 85 c-40 c - 85 c-40 c - 85 c-40 c - 85 c v cc power supply 5v 5% 5v 10% 5v 10% 5v 10% operating modes mode ce oe we ai i/o read v il v il v ih ai d out program (2) v il v ih v il ai d in 5v chip erase v il v ih v il ai standby/write inhibit v ih x (1) x x high z write inhibit x x v ih write inhibit x v il x output disable x v ih x high z high voltage chip erase v il v h (3) v il x high z product identification hardware v il v il v ih a1-a14 = v il , a9 = v h , a0 = v il manufacturer code (4) a1-a14 = v il , a9 = v h , a0 = v ih device code (4) software (5) a0 = v il manufacturer code (4) a0 = v ih device code (4) dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc 10 a i lo output leakage current v i/o = 0v to v cc 10 a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc 300 a i sb2 v cc standby current ttl ce = 2.0v to v cc 3ma i cc v cc active current f = 5 mhz; i out = 0 ma 50 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh1 output high voltage i oh = -400 a 2.4 v v oh2 output high voltage cmos i oh = -100 a; v cc = 4.5v 4.2 v
at29c256 5 ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (cl = 5 pf). 4. this parameter is characterized and is not 100% tested. input test waveforms and measurement level output test load note: 1. this parameter is characterized and is not 100% tested. ac read characteristics symbol parameter at29c256-70 at29c256-90 at29c256-12 at29c256-15 units min max min max min max min max t acc address to output delay 70 90 120 150 ns t ce (1) ce to output delay 70 90 120 150 ns t oe (2) oe to output delay 040040050070ns t df (3)(4) ce or oe to output float 025025030040ns t oh output hold from oe , ce or address, whichever occurred first 0000ns t r , t f < 5 ns pin capacitance f = 1 mhz, t = 25 c (1) symbol typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v
at29c256 6 ac byte load waveforms we controlled ce controlled ac byte load characteristics symbol parameter min max units t as , t oes address, oe set-up time 0 ns t ah address hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce )90ns t ds data set-up time 35 ns t dh ,t oeh data, oe hold time 0 ns t wph write pulse width high 100 ns
at29c256 7 program cycle waveforms (1)(2)(3) notes: 1. a6 through a14 must specify the page address during each high-to-low transition of we (or ce ). 2. oe must be high when we and ce are both low. 3. all bytes that are not loaded within the page being programmed will be indeterminate. program cycle characteristics symbol parameter min max units t wc write cycle time 10 ms t as address set-up time 0 ns t ah address hold time 50 ns t ds data set-up time 35 ns t dh data hold time 0 ns t wp write pulse width 90 ns t blc byte load cycle time 150 s t wph write pulse width high 100 ns
at29c256 8 software data protection enable algorithm (1) notes for software program code: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. data protect state will be re-activated at end of pro- gram cycle. 3. data protect state will be deactivated at end of pro- gram period. 4. 64 bytes of data must be loaded. software data protection disable algorithm (1) software protected program cycle waveform (1)(2)(3) notes: 1. a6 through a14 must specify the page address during each high-to-low transition of we (or ce ) after the software code has been entered. 2. oe must be high when we and ce are both low. 3. all bytes that are not loaded within the page being programmed will be indeterminate. load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data to page (64 bytes) (4) writes enabled (2) enter data protect state load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 20 to address 5555 load data to page (64 bytes) (4) exit data protect state (3)
at29c256 9 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 0 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 0 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns
at29c256 10 software product identification entry (1) notes for software product identification: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. a1 - a14 = v il . manufacturer code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code is 1f. the device code is dc. software product identification exit (1) load data aa to address 5555 load data 55 to address 2aaa load data 90 to address 5555 pause 10 ms enter product identification mode (2)(3)(5) load data aa to address 5555 load data 55 to address 2aaa load data f0 to address 5555 pause 10 ms exit product identification mode (4)
at29c256 11 normalized supply current vs. temperature temperature (c) -55 1.4 1.3 1.2 1.1 1.0 0.8 0.9 -25 5 35 65 95 125 n o r m a l i z e d i c c normalized supply current vs. address frequency frequency (mhz) 0 1.1 1.0 0.9 0.8 0.7 1234567 n o r m a l i z e d i c c v cc = 5v t = 25c normalized supply current vs. supply voltage supply voltage (v) 4.50 1.4 1.2 1.0 0.8 0.6 4.75 5.00 5.25 5.50 n o r m a l i z e d i c c
at29c256 12 ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 70 50 0.3 at29c256-70jc at29c256-70pc at29c256-70tc 32j 28p6 28t commercial (0 to 70 c) at29c256-70ji at29c256-70ti 32j 28t industrial (-40 to 85 c) 90 50 0.3 at29c256-90jc at29c256-90pc at29c256-90tc 32j 28p6 28t commercial (0 to 70 c) at29c256-90ji at29c256-90pi at29c256-90ti 32j 28p6 28t industrial (-40 to 85 c) 120 50 0.3 at29c256-12jc at29c256-12pc at29c256-12tc 32j 28p6 28t commercial (0 to 70 c) at29c256-12ji at29c256-12pi at29c256-12ti 32j 28p6 28t industrial (-40 to 85 c) 150 50 0.3 at29c256-15jc at29c256-15pc at29c256-15tc 32j 28p6 28t commercial (0 to 70 c) at29c256-15ji at29c256-15pi at29c256-15ti 32j 28p6 28t industrial (-40 to 85 c) package type 32j 32-lead, plastic j-leaded chip carrier (plcc) 28p6 28-lead, 0.600" wide, plastic dual inline package (pdip) 28t 28-lead, plastic thin small outline package (tsop)
at29c256 13 packaging information .045(1.14) x 45? pin no. 1 identify .025(.635) x 30? - 45? .012(.305) .008(.203) .021(.533) .013(.330) .530(13.5) .490(12.4) .030(.762) .015(.381) .095(2.41) .060(1.52) .140(3.56) .120(3.05) .032(.813) .026(.660) .050(1.27) typ .553(14.0) .547(13.9) .595(15.1) .585(14.9) .300(7.62) ref .430(10.9) .390(9.90) at contact points .022(.559) x 45? max (3x) .453(11.5) .447(11.4) .495(12.6) .485(12.3) 1.47(37.3) 1.44(36.6) pin 1 .566(14.4) .530(13.5) .090(2.29) max .005(.127) min .065(1.65) .015(.381) .022(.559) .014(.356) .065(1.65) .041(1.04) 0 15 ref .630(16.0) .590(15.0) .690(17.5) .610(15.5) .012(.305) .008(.203) .110(2.79) .090(2.29) .161(4.09) .125(3.18) seating plane .220(5.59) max 1.300(33.02) ref *controlling dimension: millimeters index mark area 0.55 (0.022) bsc 0.20 (0.008) 0.10 (0.004) 7.15 (0.281) ref 8.10 (0.319) 7.90 (0.311) 1.25 (0.049) 1.05 (0.041) 0.27 (0.011) 0.18 (0.007) 11.9 (0.469) 11.7 (0.461) 13.7 (0.539) 13.1 (0.516) 0 5 0.20 (0.008) 0.15 (0.006) ref 0.70 (0.028) 0.30 (0.012) 32j , 32-lead, plastic j-leaded chip carrier (plcc) dimensions in inches and (millimeters) jedec standard ms-016 ae 28p6 , 28-lead, 0.600" wide, plastic dual inline package (pdip) dimensions in inches and (millimeters) jedec standard ms-011 ab 28t , 28-lead, plastic thin small outline package (tsop) dimensions in millimeters and (inches)*
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